a. Field of the Invention
The present invention pertains to electrical data busses and specifically to characterizing the bus performance.
b. Description of the Background
Parallel data busses are ubiquitous in electronics and computers. In general, several data lines are read simultaneously on a specific interval known as a clock cycle. The values of the several data lines may then change for the next clock cycle. Typically, the data bits many change prior to the occurrence of the read event. If a data bit is changing during read event, an incorrect read event may occur, introducing errors into the data.
Not all of the data lines in a certain bus will turn on and off with the same timing as the other data lines. The causes may be the result of a difference in trace lengths, the amount of resistance or capacitance of the components attached to the data line, manufacturing differences, noise, crosstalk, or many other causes. As clock rates increase, electronics designers face increasing challenges in insuring that the data lines are in their proper state when the data lines are read.
It would therefore be advantageous to provide a system and method for characterizing a parallel data bus wherein the performance of the bus may be visualized. It would be further advantageous if the system and method were able to optimize performance of the bus.